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Software for processing (receiving) ARINC-429 standard signals, decoding RES-ARINC-DECORE-01

Description
  • Description:
    A software module designed to process ARINC-429 standard signals on FPGA chips. It handles data reception, decoding, processing, and command execution.
  • Technical features:
    • Developed using VHDL (VHSIC Hardware Description Language) or AHDL.
    • Output files: *.POF, *.SOF (compiled using Quartus Compiler version 8.1 or later).
    • Supports receiving configuration data from EEPROM for FPGA initialization.
    • Capable of decoding ARINC-429 data streams (32-bit words including label, data, parity bits).
    • Implements FIFO buffering for continuous data handling.
    • Supports command execution and data packaging for transmission.
    • Ensures signal processing meets ARINC-429 standard timing and frequency requirements.
  • Additional capabilities:
    • Master configuration initialization for FPGA.
    • Data verification (verify) and signal detection (detect).
    • Compatible with JTAG or dedicated programming tools for loading configuration